Optimization Of Power For Sequential Elements In Pulse Triggered Flip-Flop Using Low Power Topologies

The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. The main objective of this project is to design a Low-Power Pulse-Triggered flip-flop. Flip-flops are the major storage elements in all SOC’s of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays. The delay of the flip-flops should be minimized for efficient implementation. Here three kind of conventional pulse-triggered flip-flop are designed. First, the implicit Pulsed Data-Close to output (ip-DCO) pulse-triggered flip-flop. Second, the Modified Version of Hybrid latch flip-flop (MHLFF) and third is the Single-ended Conditional Capturing Energy Recovery (SCCER) flip-flop. These three flip-flops are studied and designed. The comparison of low power pulse triggered flip-flops between SAL ,SVL logics is carried out and the best power -delay-performance is obtained. The simulation results are obtained with Tanner simulation tool.